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cy7c027 cy7c028 32 k / 64 k 16 dual-port static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-06042 rev. *g revised august 23, 2011 32 k / 64 k 16 dual-port static ram features true dual-ported memory cells which allow simultaneous access of the same memory location 32 k 16 organization (cy7c027) 64 k 16 organization (cy7c028) 0.35 micron cmos for optimum speed and power high speed access: 15 and 20 ns low operating power active: i cc = 180 ma (typical) standby: i sb3 = 0.05 ma (typical) fully asynchronous operation automatic power down expandable data bus to 32 bits or more using master/slave chip select when using more than one device on-chip arbitration logic semaphores included to permit software handshaking between ports int flags for port-to-port communication separate upper-byte and lower-byte control dual chip enables pin select for master or slave commercial and industrial temperature ranges available in 100-pin tqfp pb-free packages available r/w l ce 0l ce 1l oe l i/o 8l ?i/o 15l i/o control address decode a 0l ?a 14/15l ce l oe l r/w l busy l i/o control ce l interrupt semaphore arbitration sem l int l m/s ub l lb l i/o 0l ?i/o 7l r/w r ce 0r ce 1r oe r i/o 8l ?i/o 15r ce r ub r lb r i/o 0l ?i/o 7r ub l lb l logic block diagram a 0l ?a 14/15l true dual-ported ram array a 0r ?a 14/15r ce r oe r r/w r busy r sem r int r ub r lb r address decode a 0r ?a 14/15r [1] [1] [2] [2] [3] [3] [4] [4] [3] [3] 15/16 8 8 15/16 8 8 15/16 15/16 notes 1. i/o 8 ?i/o 15 for 16 devices 2. i/o 0 ?i/o 7 for 16 devices 3. a 0 ?a 14 for 32k; a 0 ?a 15 for 64k devices. 4. busy is an output in master mode and an input in slave mode. cy7c02732 k / 64 k 16 dual-port static ram [+] feedback
cy7c027 cy7c028 document #: 38-06042 rev. *g page 2 of 23 functional description the cy7c027 and cy7c028 are low power cmos 32 k, 64 k 16 dual-port static rams. various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. the devices can be used as standalone 16-bit dual-port static rams or multiple devices can be combined to function as a 32-bit or wider master/slave dual-port static ram. an m/s pin is provided for implementing 32-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. application areas include interprocessor and multiprocessor designs, communications status buffering, and dual-port video/graphics memory. each port has independent control pins: dual chip enables (ce 0 and ce 1 ), read or write enable (r/w ), and output enable (oe ). two flags are provided on each port (busy and int ). busy signals that the port is trying to access the same location currently being accessed by the other port. the interrupt flag (int ) permits communication between ports or systems by means of a mail box. the semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphore logic is comprised of eight shared latches. only one side c an control the latch (semaphore) at any time. control of a sema phore indicates that a shared resource is in use. an automatic power down feature is controlled independently on each port by the chip enable pins. the cy7c027 and cy7c028 are available in 100-pin thin quad flat pack (tqfp) packages. [+] feedback
cy7c027 cy7c028 document #: 38-06042 rev. *g page 3 of 23 contents pin configurations ........................................................... 4 selection guide ................................................................ 5 pin definitions .................................................................. 5 maximum ratings ............................................................. 6 operating range ............................................................... 6 electrical characteristics ................................................. 6 capacitance ...................................................................... 7 ac test loads and waveforms ....................................... 7 switching characteristics ................................................ 8 data retention mode ........................................................ 9 timing ................................................................................ 9 switching waveforms .................................................... 10 architecture .................................................................... 16 functional description ................................................... 16 write operation ......................................................... 16 read operation ......................................................... 16 interrupts ................................................................... 16 busy .......................................................................... 16 master/slave ............................................................. 16 semaphore operation ............................................... 16 ordering information ...................................................... 19 32 k 16 asynchronous dual-port sram ............... 19 64 k 16 asynchronous dual-port sram ............... 19 ordering code definitions ..... .................................... 19 package diagram ............................................................ 20 acronyms ........................................................................ 21 document conventions ................................................. 21 units of measure ....................................................... 21 document history page ................................................. 22 sales, solutions, and legal information ...................... 23 worldwide sales and design s upport ......... .............. 23 products .................................................................... 23 psoc solutions ......................................................... 23 [+] feedback
cy7c027 cy7c028 document #: 38-06042 rev. *g page 4 of 23 pin configurations figure 1. 100-pin tqfp (top view) 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 a9r a10r a11r a12r a13r a14r ub r nc lb r ce1r sem r oe r gnd nc a15r gnd r/w r gnd i/o15r i/o14r i/o13r i/o12r i/o11r i/o10r ce 0r 58 57 56 55 54 53 52 51 cy7c027 (32 k 16) a9l a10l a11l a12l a13l a14l ub l nc lb l ce1l sem l oe l gnd nc a15l vcc r/w l gnd i/o15l i/o14l i/o13l i/o12l i/o11l i/o10l ce 0l 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 a8l a7l a6l a5l a4l a3l int l a1l nc gnd m/s a0r a1r a0l a2l busy r int r a2r a3r a4r a5r a6r a7r a8r busy l 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 nc i/o9r i/o8r i/o7r vcc i/o6r i/01r i/o4r i/o2r gnd i/o0l i/o2l i/o3l i/o3r i/o5r i/o1l gnd i/o4l i/o5l i/o6l i/o7l vcc i/o8l i/o9l i/o0r 33 32 31 30 29 28 27 26 cy7c028 (64 k 16) [5] [5] note 5. this pin is nc for cy7c027. [+] feedback
cy7c027 cy7c028 document #: 38-06042 rev. *g page 5 of 23 selection guide parameter cy7c027/cy7c028 -15 cy7c027/cy7c028 -20 unit maximum access time 15 20 ns typical operating current 190 180 ma typical standby current for i sb1 (both ports ttl level) 50 45 ma typical standby current for i sb3 (both ports cmos level) 0.05 0.05 ma pin definitions left port right port description ce 0l , ce 1l ce 0r , ce 1r chip enable (ce is low when ce 0 ? v il and ce 1 ?? v ih ) r/w l r/w r read/write enable oe l oe r output enable a 0l ?a 15l a 0r ?a 15r address (a 0 ?a 14 for 32k; a 0 ?a 15 for 64k devices) i/o 0l ?i/o 15l i/o 0r ?i/o 15r data bus input/output (i/o 0 ?i/o 15 for 16 devices) sem l sem r semaphore enable ub l ub r upper byte select (i/o 8 ?i/o 15 for 16 devices) lb l lb r lower byte select (i/o 0 ?i/o 7 for 16 devices) int l int r interrupt flag busy l busy r busy flag m/s master or slave select v cc power gnd ground nc no connect [+] feedback
cy7c027 cy7c028 document #: 38-06042 rev. *g page 6 of 23 maximum ratings exceeding maximum ratings [6] may shorten the useful life of the device. user guidelines are not tested. storage temperature ................ ............... ?65 c to +150 c ambient temperature with power applied ........... ............... ............... ?55 c to +125 c supply voltage to ground potential .............?0.3 v to +7.0 v dc voltage applied to outputs in high z state ...................................... ?0.5 v to +7.0 v dc input voltage [7] ...........................................?0.5 v to +7.0 v output current into outputs (low) ............................ 20 ma static discharge voltage .......................................... > 1100v latch-up current ................................................... > 200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 5 v ? 10% industrial [8] ?40 c to +85 c 5 v ? 10% electrical characteristics over the operating range symbol parameter cy7c027/cy7c028 unit -15 -20 min typ max min typ max v oh output high voltage (v cc = min, i oh = ?4.0 ma) 2.4 ? ? 2.4 ? ? v v ol output low voltage (v cc = min, i oh = +4.0 ma) ? 0.4 ? 0.4 v v ih input high voltage 2.2 ? 2.2 ? v v il input low voltage ? 0.8 ? 0.8 v i oz output leakage current ?10 10 ?10 10 ? a i cc operating current (v cc = max, i out = 0 ma) outputs disabled commercial ? 190 280 ? 180 265 ma industrial [8] ? 305 290 ma i sb1 standby current (both ports ttl level) ce l & ce r ? v ih , f = f max commercial 50 70 45 65 ma industrial [8] ?6080ma i sb2 standby current (one port ttl level) ce l | ce r ? v ih , f = f max commercial 120 180 110 160 ma industrial [8] ? 125 175 ma i sb3 standby current (both ports cmos level) ce l & ce r ? v cc ? 0.2 v, f = 0 commercial 0.05 0.5 0.05 0.5 ma industrial [8] ? 0.05 0.5 ma i sb4 standby current (one port cmos level) ce l | ce r ? v ih , f = f max [9] commercial 110 160 100 140 ma industrial [8] ? 115 155 ma notes 6. the voltage on any input or i/o pin cann ot exceed the power pin during power up. 7. pulse width < 20 ns. 8. industrial parts are available in cy7c028 only. 9. f max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. this applies only to inputs at cmos level standby i sb3. [+] feedback
cy7c027 cy7c028 document #: 38-06042 rev. *g page 7 of 23 capacitance parameter [10] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0 v 10 pf c out output capacitance 10 pf ac test loads and waveforms figure 2. ac test loads and waveforms 3.0 v gnd 90% 90% 10% 3ns 3 ns 10% all input pulses (a) normal load (load 1) r1 = 893 ? 5 v output r2 = 347 ? c =30 pf v th = 1.4 v output c= 30 pf (b) thvenin equivalent (load 1) (c) three-state delay (load 2) r1 = 893 ? r2 = 347 ? 5 v output c= 5pf r th = 250 ? ? ? (used for t cklz , t olz , & t ohz including scope and jig) note 10. tested initially and after any design or proces s changes that may affect these parameters. [+] feedback
cy7c027 cy7c028 document #: 38-06042 rev. *g page 8 of 23 switching characteristics over the operating range parameter [11] description cy7c027/cy7c028 unit -15 -20 min max min max read cycle t rc read cycle time 15 ? 20 ? ns t aa address to data valid ? 15 ? 20 ns t oha output hold from address change 3 ? 3 ? ns t ace [12] ce low to data valid ? 15 ? 20 ns t doe oe low to data valid ? 10 ? 12 ns t lzoe [13, 14, 15] oe low to low z 3 ? 3 ? ns t hzoe [13, 14, 15] oe high to high z ? 10 ? 12 ns t lzce [13, 14, 15] ce low to low z 3 ? 3 ? ns t hzce [13, 14, 15] ce high to high z ? 10 ? 12 ns t pu [15] ce low to power up 0 ? 0 ? ns t pd [15] ce high to power down ? 15 ? 20 ns t abe [12] byte enable access time ? 15 ? 20 ns write cycle t wc write cycle time 15 ? 20 ? ns t sce [12] ce low to write end 12 ? 15 ? ns t aw address valid to write end 12 ? 15 ? ns t ha address hold from write end 0 ? 0 ? ns t sa [12] address setup to write start 0 ? 0 ? ns t pwe write pulse width 12 ? 15 ? ns t sd data setup to write end 10 ? 15 ? ns t hd data hold from write end 0 ? 0 ? ns t hzwe [14, 15] r/w low to high z ? 10 ? 12 ns t lzwe [14, 15] r/w high to low z 3 ? 3 ? ns t wdd [16] write pulse to data delay ? 30 ? 45 ns t ddd [16] write data valid to read data valid ? 25 ? 30 ns busy timing [17] t bla busy low from address match ? 15 ? 20 ns t bha busy high from address mismatch ? 15 ? 20 ns t blc busy low from ce low ? 15 ? 20 ns t bhc busy high from ce high ?15?17ns t ps port setup for priority 5 ? 5 ? ns notes 11. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3.0 v, and output loading of the specified i oi /i oh and 30 pf load capacitance. 12. to access ram, ce = l, ub = l, sem = h. to access semaphore, ce = h and sem = l. either condition must be valid for the entire t sce time. 13. at any given temperature and voltag e condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 14. test conditions used are load 2. 15. this parameter is guaranteed by desig n, but it is not production tested. 16. for information on port-to-port delay through ram cells from writing port to reading port, refer to figure 11 on page 13 . 17. test conditions used are load 1. [+] feedback
cy7c027 cy7c028 document #: 38-06042 rev. *g page 9 of 23 data retention mode the cy7c027 and cy7c028 are designed with battery backup in mind. data retention voltage and supply current are guaranteed over temp erature. the following rules ensure data retention: 1. chip enable (ce ) must be held high during data retention, within v cc to v cc ? 0.2 v. 2. ce must be kept between v cc ? 0.2 v and 70% of v cc during the power up and power down transitions. 3. the ram can begin operation > t rc after v cc reaches the minimum operating voltage (4.5 v). t wb r/w high after busy (slave) 0?0?ns t wh r/w high after busy high (slave) 13 ? 15 ? ns t bdd [18] busy high to data valid ? 15 ? 20 ns interrupt timing [19] t ins int set time ?15?20ns t inr int reset time ?15?20ns semaphore timing t sop sem flag update pulse (oe or sem )10?10?ns t swrd sem flag write to read time 5 ? 5 ? ns t sps sem flag contention window 5 ? 5 ? ns t saa sem address access time ? 15 ? 20 ns switching characte ristics (continued) over the operating range parameter [11] description cy7c027/cy7c028 unit -15 -20 min max min max timing figure 3. timing parameter test conditions [20] max unit icc dr1 at vcc dr = 2 v 1.5 ma data retention mode 4.5 v 4.5 v v cc ? ? 2.0 v v cc to v cc ? 0.2 v v cc ce t rc v ih notes 18. t bdd is a calculated parameter and is the greater of t wdd ?t pwe (actual) or t ddd ?t sd (actual). 19. test conditions used are load 1. 20. ce = v cc , v in = gnd to v cc , t a = 25 c. this parameter is guaranteed but not tested. [+] feedback
cy7c027 cy7c028 document #: 38-06042 rev. *g page 10 of 23 switching waveforms figure 4. read cycle no. 1 (either port address access) [21, 22, 23] figure 5. read cycle no. 2 (either port ce /oe access) [21, 24, 25] figure 6. read cycle no. 3 (either port) [21, 23, 24, 25] t rc t aa t oha data valid previous data valid data out address t oha t ace t lzoe t doe t hzoe t hzce data valid t lzce t pu t pd i sb i cc data out oe ce and lb or ub current ub or lb data out t rc address t aa t oha ce t lzce t abe t hzce t hzce t ace t lzce notes 21. r/w is high for read cycles. 22. device is continuously selected ce = v il and ub or lb = v il . this waveform cannot be used for semaphore reads. 23. oe = v il . 24. address valid prior to or coincident with ce transition low. 25. to access ram, ce = v il , ub or lb = v il , sem = v ih . to access semaphore, ce = v ih , sem = v il . [+] feedback
cy7c027 cy7c028 document #: 38-06042 rev. *g page 11 of 23 figure 7. write cycle no. 1 (r/w controlled timing) [26, 27, 28, 29] figure 8. write cycle no. 2 (ce controlled timing) [26, 27, 28, 33, 34] switching waveforms (continued) t aw t wc t pwe t hd t sd t ha ce r/w oe data out data in address t hzoe t sa t hzwe t lzwe [32] [32] [29] [30, 31] note 33 note 33 t aw t wc t sce t hd t sd t ha ce r/w data in address t sa [30, 31] notes 26. r/w must be high during all address transitions. 27. a write occurs during the overlap (t sce or t pwe ) of a low ce or sem and a low ub or lb . 28. t ha is measured from the earlier of ce or r/w or (sem or r/w ) going high at the end of write cycle. 29. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of t pwe or (t hzwe + t sd ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t sd . if oe is high during an r/w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t pwe . 30. to access ram, ce = v il , sem = v ih . 31. to access upper byte, ce = v il , ub = v il , sem = v ih . to access lower byte, ce = v il , lb = v il , sem = v ih . 32. transition is measured ? 500 mv from steady state with a 5 pf load (including sc ope and jig). this parameter is sampled and not 100% tested. 33. during this period, the i/o pins are in the output state, and input signals must not be applied. 34. if the ce or sem low transition occurs simultaneously with or after the r/w low transition, the outputs remain in the high impedance state. [+] feedback
cy7c027 cy7c028 document #: 38-06042 rev. *g page 12 of 23 figure 9. semaphore read after write timing, either side [35] figure 10. timing diagra m of semaphore contention [36, 37, 38] switching waveforms (continued) t sop t saa valid adress valid adress t hd data in valid data out valid t oha t aw t ha t ace t sop t sce t sd t sa t pwe t swrd t doe write cycle read cycle oe r/w i/o 0 sem a 0 ?a 2 match t sps a 0l ?a 2l match r/w l sem l a 0r ?a 2r r/w r sem r notes 35. ce = high for the duration of the above timing (both write and read cycle). 36. i/o 0r = i/o 0l = low (request semaphore); ce r = ce l = high. 37. semaphores are reset (availabl e to both ports) at cycle start. 38. if t sps is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable . [+] feedback
cy7c027 cy7c028 document #: 38-06042 rev. *g page 13 of 23 figure 11. timing diagram of read with busy (m/s = high) [39] figure 12. write timing with busy input (m/s = low) switching waveforms (continued) valid t ddd t wdd match match r/w r data in r data outl t wc address r t pwe valid t sd t hd address l t ps t bla t bha t bdd busy l t pwe r/w busy t wb t wh note 39. ce l = ce r = low. [+] feedback
cy7c027 cy7c028 document #: 38-06042 rev. *g page 14 of 23 figure 13. busy timing diagram no.1 (ce arbitration) [40] figure 14. busy timing diagra m no. 2 (address arbitration) [40] switching waveforms (continued) address match t ps t blc t bhc address match t ps t blc t bhc ce r valid first: address l,r busy r ce l ce r busy l ce r ce l address l,r ce l valid first: address match t ps address l busy r address mismatch t rc or t wc t bla t bha address r address match address mismatch t ps address l busy l t rc or t wc t bla t bha address r right address valid first: left address valid first: note 40. if t ps is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side busy is asserted. [+] feedback
cy7c027 cy7c028 document #: 38-06042 rev. *g page 15 of 23 figure 15. interrupt timing diagrams switching waveforms (continued) write 7fff (ffff for cy7c028) t wc right side clears int r : t ha read 7fff t rc t inr write 7ffe (fffe for cy7c028) t wc right side sets int l : left side sets int r : left side clears int l : read 7ffe t inr t rc address r ce l r/w l int l oe l address r r/w r ce r int l address r ce r r/w r int r oe r address l r/w l ce l int r t ins t ha t ins (ffff for cy7c028) (fffe for cy7c028) [41] [42] [42] [42] [41] [42] notes 41. t ha depends on which enable pin (ce l or r/w l ) is deasserted first. 42. t ins or t inr depends on which enable pin (ce l or r/w l ) is asserted last. [+] feedback
cy7c027 cy7c028 document #: 38-06042 rev. *g page 16 of 23 architecture the cy7c027 and cy7c028 consist of an array of 32k and 64k words of 16 bits each of dual-port ram cells, i/o and address lines, and control signals (ce , oe , r/w ). these control pins permit independent access for reads or writes to any location in memory. to handle simultaneous writes/reads to the same location, a busy pin is provided on each port. two interrupt (int ) pins can be used for port-to-port communication. two semaphore (sem ) control pins are used for allocating shared resources. with the m/s pin, the devices can function as a master (busy pins are outputs) or as a slave (busy pins are inputs). the devices also have an automatic power down feature controlled by ce . each port is provided with its own output enable control (oe ), which allows data to be read from the device. functional description write operation data must be set up for a duration of t sd before the rising edge of r/w to guarantee a valid write. a write operation is controlled by either the r/w pin (see figure 7 on page 11 ) or the ce pin (see figure 8 on page 11 ). required inputs for non-contention operations are summarized in table 1 . if a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is r ead on the output; otherwise the data read is not deterministic. data is valid on the port t ddd after the data is presen ted on the other port. read operation when reading the device, the user must assert both the oe and ce pins. data is available t ace after ce or t doe after oe is asserted. if the user wishes to access a semaphore flag, then the sem pin must be asserted instead of the ce pin, and oe must also be asserted. interrupts the upper two memory locations may be used for message passing. the highest memory location (7fff for the cy7c027, ffff for the cy7c028) is the mailbox for the right port and the second-highest memory location (7ffe for the cy7c027, fffe for the cy7c028) is the mailbox for the left port. when one port writes to the other port?s mailbox, an interrupt is generated to the owner. the interrupt is reset when the owner reads the contents of the mailbox. the message is user defined. each port can read the other po rt?s mailbox without resetting the interrupt. the active state of th e busy signal (to a port) prevents the port from setting the interrupt to the winning port. also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. if an application does not require message passing, do not connect the interrupt pin to the processor?s interrupt request input pin. the operation of the interrupts and their interaction with busy is summarized in table 2 . busy the cy7c027 and cy7c028 provide on-chip arbitration to resolve simultaneous memory location access (contention). if both ports? ce s are asserted and an address match occurs within t ps of each other, the busy logic determines which port has access. if t ps is violated, one port definitely gains permission to the location, but it is not predictable which port gets that permission. busy is asserted t bla after an address match or t blc after ce is taken low. master/slave a m/s pin is provided to expand the word width by configuring the device as either a master or a slave. the busy output of the master is connected to the busy input of the slave. this allows the device to interface to a master device with no external components. writing to slave devices must be delayed until after the busy input has settled (t blc or t bla ), otherwise, the slave chip may begin a write cycle durin g a contention si tuation. when tied high, the m/s pin allows the device to be used as a master and, therefore, the busy line is an output. busy can then be used to send the arbitration outcome to a slave. semaphore operation the cy7c027 and cy7c028 provide eight semaphore latches, which are separate from the dual-port memory locations. semaphores are used to reserve resources that are shared between the two ports.the state of the semaphore indicates that a resource is in use. for example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. the left port then verifi es its success in setting the latch by reading it. after writing to the semaphore, sem or oe must be deasserted for t sop before attempting to read the semaphore. the semaphore value is available t swrd + t doe after the rising edge of the semaphore write. if the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assume s the right port has control and continues to poll the semaphore. when the right side has relinquished control of the sema phore (by writing a one), the left side succeeds in gaining control of the semaphore. if the left side no longer requires the semaphore, a one is written to cancel its request. semaphores are accessed by asserting sem low. the sem pin functions as a chip select for the semaphore latches (ce must remain high during sem low). a 0?2 represents the semaphore address. oe and r/w are used in the same manner as a normal memory access. when writing or reading a semaphore, the other addre ss pins have no effect. when writing to the semaphore, only i/o 0 is used. if a zero is written to the left port of an available semaphore, a one appears at the same semaphore address on the right port. that semaphore can now only be modified by the side showing zero (the left port in this case). if the left port now relinquishes control by writing a one to the semaphore, the semaphore is set to one for both sides. however, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. ta b l e 3 shows sample semaphore operations. when reading a semaphore, all sixteen/eighteen data lines output the semaphore value. the read value is latched in an [+] feedback
cy7c027 cy7c028 document #: 38-06042 rev. *g page 17 of 23 output register to prevent the semaphore from changing state during a write from the other port. if both ports attempt to access the semaphore within t sps of each other, the semaphore is definitely obtained by one side or the other, but there is no guarantee which side controls the semaphore. table 1. non-contending read/write inputs outputs ce r/w oe ub lb sem i/o 8 ? i/o 15 i/o 0 ? i/o 7 operation h x x x x h high z high z deselected: power down x x x h h h high z high z deselected: power down l l x l h h data in high z write to upper byte only l l x h l h high z data in write to lower byte only l l x l l h data in data in write to both bytes l h l l h h data out high z read upper byte only l h l h l h high z data out read lower byte only l h l l l h data out data out read both bytes x x h x x x high z high z outputs disabled h h l x x l data out data out read data in semaphore flag x h l h h l data out data out read data in semaphore flag h x x x l data in data in write d in0 into semaphore flag x x h h l data in data in write d in0 into semaphore flag l x x l x l not allowed l x x x l l not allowed table 2. interrupt operation example (assumes busy l = busy r = high) [43] left port right port function r/w l ce l oe l a 0 l ?14 l int l r/w r ce r oe r a 0r?14r int r set right int r flagl lx 7fff xxxx x l [44] reset right int r flag x x x x x x l l 7fff h [45] set left int l flag x x x x l [45] llx7ffex reset left int l flag x l l 7ffe h [44] xxxxx notes 43. a 0l?15l and a 0r?15r , ffff/fffe for the cy7c028. 44. if busy l = l, then no change. 45. if busy r = l, then no change. [+] feedback
cy7c027 cy7c028 document #: 38-06042 rev. *g page 18 of 23 table 3. semaphore operation example function i/o 0 ? i/o 15 left i/o 0 ? i/o 15 right status no action 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token right port writes 0 to semaphore 0 1 no change. right side has no write access to semaphore left port writes 1 to semaphore 1 0 r ight port obtains semaphore token left port writes 0 to semaphore 1 0 no change. left port has no write access to semaphore right port writes 1 to semaphore 0 1 left port obtains semaphore token left port writes 1 to semaphore 1 1 semaphore free right port writes 0 to semaphore 1 0 right port has semaphore token right port writes 1 to semaphore 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token left port writes 1 to semaphore 1 1 semaphore free [+] feedback
cy7c027 cy7c028 document #: 38-06042 rev. *g page 19 of 23 ordering information ordering code definitions 32 k 16 asynchronous dual-port sram speed (ns) ordering code package name package type operating range 20 CY7C027-20AXC a100 100-pin thin quad flat pack (pb-free) commercial 64 k 16 asynchronous dual-port sram speed (ns) ordering code package name package type operating range 15 cy7c028-15axc a100 100-pin thin quad flat pack (pb-free) commercial cy7c028-15ai a100 100-pin thin quad flat pack industrial cy7c028-15axi a100 100-pin thin q uad flat pack (pb-free) industrial temperature range: x = c or i c = commercial; i = industrial x = pb-free (rohs compliant) package type: a = 100-pin tqfp speed grade: 20 ns or 15 ns depth: x = 7 or 8 7 = 32k; 8 = 64k width: 02 = 16 technology code: c = cmos marketing code: 7 = dual port sram company id: cy = cypress c cy 02 - xx x x x x 7 [+] feedback
cy7c027 cy7c028 document #: 38-06042 rev. *g page 20 of 23 package diagram figure 16. 100-pin tqfp (14 14 1.4 mm) a100sa, 51-85048 51-85048 *e [+] feedback
cy7c027 cy7c028 document #: 38-06042 rev. *g page 21 of 23 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory tqfp thin quad flat pack ttl transistor-transistor logic symbol unit of measure c degree celsius mhz mega hertz a micro amperes ma milli amperes mm milli meter ns nano seconds ? ohms % percent pf pico farad vvolts [+] feedback
cy7c027 cy7c028 document #: 38-06042 rev. *g page 22 of 23 document history page document title: cy7c027/cy7c028, 32 k / 64 k 16 dual-port static ram document number: 38-06042 rev. ecn no. orig. of change submission date description of change ** 110190 szv 09/29/01 change from spec number: 38-00666 to 38-06042 *a 122292 rbi 12/27/02 power up requirements added to maximum ratings information *b 236765 ydt 6/23/04 removed cross information from features section *c 377454 pcx see ecn added pb-free logo added pb-free parts to ordering information: CY7C027-20AXC, cy7c028-12axc, cy7c028-15axc, cy7c028-15ai, cy7c028-15axi *d 2623540 vkn/pyrs 12/17/08 added cy7c027-15axi in the ordering information table *e 2897217 rame 03/22/2010 updated ordering information updated package diagram *f 3111417 admu 12/15/2010 added ordering code definitions . *g 3352028 admu 08/23/2011 updated features (removed cy7c037/cy7c038 information and also removed -12 speed bin information). updated functional description (removed cy7c037/cy7c038 information). updated pin configurations (removed cy7c037/cy7c038 information). updated selection guide (removed cy7c037/cy7c038 information and also removed -12 speed bin information). updated electrical characteristics (removed cy7c037/cy7c038 information and also removed -12 speed bin information). updated ac test loads and waveforms (removed -12 speed bin information). updated switching characteristics (removed cy7c037/cy7c038 information and also removed -12 speed bin information). updated package diagram . added acronyms and units of measure . updated in new template. [+] feedback
document #: 38-06042 rev. *g revised august 23, 2011 page 23 of 23 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c027 cy7c028 ? cypress semiconductor corporation, 2001-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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